(1) Field of the Invention
The present invention relates to a digital signal processor for processing inputted right channel data (hereinafter called "R-ch data") and left channel data (hereinafter called "L-ch data") of an audio signal and, more particularly, to a digital signal processor which can simultaneously process the R-ch data and L-ch data of the audio signal.
(2) Description of the Prior Art
A typical conventional digital signal processor to which the present invention relates is shown in FIG. 1. As shown in FIG. 1, the conventional digital processor comprises: an input/output circuit (SIO) 10 for receiving input data DI and for outputting output data DO; a data memory unit 1 for storing an internal data; arithmetic circuit 2 for performing such process as a digital filtering process on the input data DI; a data delay control circuit 4 for controlling an external memory 5 for delaying the data; and a microprogram control circuit 3 for controlling the data memory unit 1, the arithmetic circuit 2 and the data delay control circuit 4. Specifically, the data input/output circuit (SIO) 10 includes a converter circuit (SR) 11 for converting the data from "serial" to "parallel" in its data format for the input data or for converting the data from "parallel" to "serial" for the output data; an input latch circuit (SI) 12 for latching or holding the input data DI; an output latch circuit (SO) 13 for latching or holding the output data DO; and an edge detection circuit (ED) 14.
Now, referring to a timing chart of FIG. 2, an actual operation of the conventional digital signal processor described above will be explained. First, the input data DI inputted to the data input/output circuit 10 is converted from serial data to parallel data. At this time, control signal BCLK is supplied from outside as a clock signal. A signal LRCK indicates whether the input/output data is L-ch data or R-ch data. Specifically, its "L" level designates the L-ch data whereas its "H" level designates the R-ch data. The control signal LRCK is edge-detected by the edge detection circuit (ED) 14, and the above input data DI, which having been converted into the parallel data by the converter circuit 11, is latched in the input latch circuit 12 at the timing of the detected edge. The signal processing for the input data DI latched in the input latch circuit 12 is started at the rising edge timing of the control signal LRCK. Thus, the input data is subjected to the digital filtering processing by the arithmetic circuit 2 and the digital delay processing by data transfer for the external memory 5 through the data delay control circuit 4. In the conventional signal processor, it should be noted that the above processing is performed sequentially and individually for the L-ch data and the R-ch data. The result of signal processing performed as above is latched in the output latch circuit 13 through an internal bus 20.
The above signal processing process is continued until the rising edge timing of the succeeding control signal LRCK. Further, the data latched in the output latch circuit 13 is loaded into the conversion circuit 11 in response to the timing of the edge signal E from the edge detection circuit 14, and after the loaded data is converted from parallel to serial data in its data format, it is outputted as the output data DO. Thus, special sound effects such as a reflected sound and an echo sound can be realized by the above signal processing steps.
However, in the above conventional digital signal processor, although it processes the R-ch data after the process on the L-ch data has been completed, it does not follow that, upon completion of the processing for the L-ch data, a new R-ch data has necessarily been latched in the input latch circuit 12.
Therefore, as the case may be, the processing for the R-ch data cannot be started until the falling edge timing of the signal LRCK in response to which the R-ch data is latched into the input latch circuit 12. In contrast, if the processing for the L-ch data takes so long a time that it is not completed until the falling edge timing of the signal LRCK, the changing point of the signal LRCK does not come while the L-ch data is latched in the output latch circuit 13, so that the L-ch data will not be outputted as the output data DO. As a result, in the conventional digital signal processor, it is to be noted that the signal processing time for the L-ch data and the R-ch data cannot be allowed to be longer than a half clock cycle of the signal LRCK. This is a problem with the conventional digital signal processor to be solved by the present invention.